Traditional silicon-on-insulator (SOI) integrated circuits are formed on SOI substrates. SOI substrates typically have a thin layer of silicon, also known as the active layer, disposed on an insulator layer such as a buried oxide layer (BOX). The insulator layer or the buried oxide layer is provided on a silicon substrate. Active devices, such as transistors, are provided in active regions formed within the silicon layer or the active layer. The size and placement of the active regions are defined by isolation regions, such as shallow trench isolation (STI) regions. Active devices in the active regions are isolated from the substrate by the BOX layer. Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.
There are generally two types of SOI transistors: partially-depleted (PD) SOI transistor and fully-depleted (FD) SOI transistor. A PD-SOI transistor is formed in an active region with an active layer thickness that is larger than the maximum depletion width. The PD-SOI transistor therefore has a partially depleted body. PD-SOI transistors have the merit of being highly manufacturable, but they suffer from floating body effects. Digital circuits which typically have higher tolerance for floating body effects may employ PD-SOI transistors. A FD-SOI transistor is formed in an active region with an active layer thickness that is smaller than the maximum depletion width. FD-SOI transistors avoid problems of floating body effects with the use of a thinner active layer thickness or a lighter body doping. Generally, analog circuitry performs better when designed using FD-SOI devices than using PD-SOI devices. Since analog and digital circuits may be formed on the same SOI chip, it is advantageous to provide SOI chips with regions suited for digital circuitry and regions suited for analog circuitry. Therefore, it is useful to provide at least two different silicon films or active layer thicknesses on SOI chips. Regions with very thin silicon films may be employed for FD-SOI devices while regions with thicker silicon films may be used for PD-SOI devices. The availability of at least two different silicon films or active layer thicknesses also offers increased flexibility in circuit and device design.
U.S. Pat. No. 5,952,695, issued to Ellis-Monaghan et al, describes a silicon-on-insulator double film structure where a selected region of the active layer is epitaxially grown to a second thickness after device isolation regions are formed. In the patent, the thickness of the epitaxial layer is limited and cannot be too large as it potentially overgrows laterally into the isolation regions and may render isolation regions ineffective.
U.S. Pat. No. 6,222,234B1, issued to Ima, describes a method of forming partially and fully depleted SOI devices on a common substrate. In the patent, two regions of the active layers with different thicknesses are formed after the isolation regions are formed. An active region with a thinner silicon layer is provided for fully-depleted devices, while an active region with a thicker silicon layer is provided for partially-depleted devices.
U.S. Pat. No. 6,414,355B1, issued to An et al, describes a structure for silicon-on-insulator chips with an active layer of non-uniform thickness. U.S. Pat. No. 6,448,114B1, issued to An et al, described several methods of forming silicon-on-insulator chips with a silicon layer or an active layer of non-uniform thickness. The silicon layer or active layer with non-uniform thickness is formed prior to providing isolation structures. In one embodiment of the invention, a selected region of the active layer is etched to form a region with thinner active layer. In another embodiment of the invention, a selected region of the active layer is epitaxially grown to form a region with a thicker active layer. Both U.S. Pat. Nos. 6,414,355B1 and 6,448,114B1 do not address the issue of forming isolation regions for an SOI chip with multiple active layer thicknesses.
Referring initially to FIGS. 1A-1B, wherein crosssections of an example of a silicon-on-insulator (SOI) chip 10 is illustrated. FIG. 1A shows a conventional silicon-on-insulator (SOI) substrate 12 where an insulator layer 14 electrically isolates a silicon active layer 16 from the silicon substrate 12. In the SOI chip 10, as shown in FIG. 1B, the SOI substrate 12 is processed to form a plurality of active regions 18,20 in the active layer 16. active devices 22, such as transistors and diodes, may be formed in the active regions 18,20. Active regions 18,20 are electrically isolated from each other by isolation regions 26. Isolation regions 26 may, for example, be formed of shallow trench isolations. The conventional SOI chip 10 of FIG. 1B features an active layer 16 of uniform thickness. The uniform active layer thickness and the planar surface 28 of the SOI substrate 10 simplify the formation process of the isolation regions 26. At present, commercial products using SOI technology employ a uniform active layer thickness and shallow trench isolation.
It is advantageous to provide at least two different silicon film thicknesses on the SOI substrate. Referring now to FIG. 2A, a cross-section of a processed SOI substrate 10 with two different silicon films or active layer thicknesses is illustrated. In the SOI substrate 10 of FIG. 2A, the active layer 16, with multiple active layer thicknesses, is formed prior to the formation of isolation regions 26. In a first region 32 of the active layer 26, the active layer 26 has a first thickness tSi1. In a second region 34 of the active layer 16, the active layer has a second thickness tSi2. It is obvious that this may be extended to include additional regions with additional silicon film thicknesses, for example, a third region 34 of the active layer 16 with a third thickness tSi3, and so on. The availability of at least two different active layer thicknesses offers the option of using a thinner active layer thickness for devices such as fully-depleted SOI transistors and a thicker active layer thickness for devices such as partially-depleted SOI transistors. Active regions with thicker active layer thickness may also be used for forming devices like diodes or lubistors, the current drive of which is proportional of the active layer thickness. For example, diodes or lubistors are used in SOI circuits for electrostatic discharge (ESD) protection.
The employment of an active layer 16 with at least two thicknesses may result in a non-planar silicon surface 28, as schematically illustrated in FIG. 2A. Due to the non-planar nature of the silicon surface, it is difficult to provide isolation regions 26 in different active regions 18,20 with different active layer thicknesses. That is, it is difficult to form the isolation regions as depicted in the cross-section of FIG. 2B. Firstly, the isolation trench depths of FIG. 2B differ in different regions. Secondly, the top surface of the isolation region is provided at different heights. Since isolation structures such as shallow trench isolation utilizes chemical mechanical polishing (CMP) to achieve planarity in the top surface of the isolation regions, CMP may not be directly applied to achieve the isolation structure shown in FIG. 2B.
It is therefore an object of the present invention to provide a method for forming isolation regions for SOI chips with multiple active layer thicknesses.
It is another object of the present invention to provide mesa isolation in a portion of an SOI chip with multiple active layer thicknesses.
It is a further object of the invention to provide conventional isolation regions, such as shallow trench isolation regions, in a portion of an SOI chip with multiple active layer thicknesses.
It is still another object of the invention to provide mesa isolation in a plurality of active regions with different active layer thicknesses.